Because of a project I am planning to start in the near future, I was looking for a good, modern, digital logic design suite that was
I considered several options, but none of them were good enough. I looked at extending logisim but its total lack of documentation and weird design choices made this infeasible.
As a result of this I have started working on my own software for this purpose, I am planning to make it have at least these features:
- Timing analysis
- Data level signal inspection ( grouping buses and showing the actual value instead of 2^N high/low values )
- Netlist export
- Eurocard layout editor
- Schematic entry
I have first started work on the circuit representation and simulator, the simulator is an event driven design which attempts to allow efficient, yet accurate modeling of large designs.
The project is written in Java, as it is an easy language for application development.
GitHub Project: https://github.com/peterbjornx/openlogiceda
Progress:January 9, 2017 - First Simulator tests
A circuit with two clocks and an AND gate: ( notice the propagation delay ):January 12, 2017 - Working on the component symbol editor
Testing pin placement,
Functions already implemented: Undo/Redo, Copy, Delete, Move, Rotate, Add, Context menu, Select, Multiple select, Save, Open, Edit properties