If you're using the local APIC, you can check its ISR register to see if the interrupt is hardware generated. You can also do that for the legacy PIC, however it is not advisable to do so, as reads from the PIC need to go through the system bus and chipset and are much slower than reads from the APIC.
Checking the instruction is not sound as an hardware IRQ might trigger at an "int" instruction boundary.
The IDT has bits that determine the privilege level that is require to invoke each vector using the "int" instruction. The CPU itself only generates faults (i.e. vector number < 32).
_________________ managarm: Microkernel-based OS capable of running a Wayland desktop (Discord: https://discord.gg/7WB6Ur3). My OS-dev projects: [mlibc: Portable C library for managarm, qword, Linux, Sigma, ...] [LAI: AML interpreter] [xbstrap: Build system for OS distributions].
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