BenLunt wrote:
I am guessing you are asking what is the difference between the Local APIC and the I/O APIC.
Each processor core will have a Local APIC. This is the hardware that handles the interrupt portion for the core. Each Local APIC has an ID and has hardware to send messages to other Local APICs. The I/O APIC is the hardware that handles the interrupt portion of the attached devices, in turn sending these interrupts to the Local APICs. All are on an APIC Bus, all connected to one another. Each processor/core capable of handling interrupts will have a Local APIC. Usually, there is only one I/O APIC having up to 24 interrupt vectors. However, there can be more than one I/O APIC.
The vector map in the I/O APIC is used to send the external interrupt to a specified Local APIC. For example, if you have two processor cores, each with one Local APIC, you can send the Timer interrupt to the first and the keyboard interrupt to the second.
If you only have one processor/core, you send each external interrupt to the same Local APIC. If two interrupts are pending, the first one goes through while the second waits until you have sent the EOI for the first one. Interrupts are not lost.
On a slightly different note, each Local APIC may and might have a timer attached. If you enable and use this timer, the Local APIC handles this interrupt locally never making it out to the I/O APIC. With this in mind, each processor/core can have its own timer, kind of like each processor/core having its own INT 0 capabilities.
There are other things you must know too. For example, the I/O APIC now will have vector redirection for ISA interrupts. The ISA's INT0 timer will most likely be redirected to vector 2. If you do not handle these redirections, when you watch for vector 0 to fire, you will be waiting a long time. See the ACPI or Multi-Processor specification for redirections.
The Local APICs also handle the processor initialization process with each processor starting out in real mode just like the first processor. Something that you must remember, each processor must be moved to protected mode or what ever mode you will be working with for that processor before it can handle interrupts.
I am sure I have missed something, and there are others here that can shed some more light on the subject, but this should get you started.
Ben
Thanks so much you answered all my questions that have after I read the Intel's manual.
Can you tell my now which is the problem with this APIC timer init code (qemu crash):
Code:
mov ebx,0xFEE003E0
mov [ebx],dword 0x3
mov ebx,0xFEE00380
mov [ebx],dword 0x100
mov ebx,0xFEE00320
mov [ebx],dword 0x20040
And 3 small question for the end at address 0xFEE00000 there exists local APIC registers right?
Also to send interrupt from an local APIC to another I will use the 0xFEE00300-0xFEE00310 (ICR) register?
If I send EOI but the IF flag isn't set the next interrupt will lost?