Joined: Sat May 20, 2017 1:25 am Posts: 51 Location: PCI bus: 3, slot: 9, function: 5
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I have a simple question what is the problem that the CPU have when it going to the ring 0 and it needs tss? Another similar question, I have 6 descriptions on gdt: 1) the null description on relative address 0x00 2) the ring 0 code description on relative address 0x08 3) the ring 0 data description on relative address 0x10 4) the ring 3 code description on relative address 0x18 5) the ring 3 data description on relative address 0x20 6) the tss description on relative address 0x28 so on kernel mode I am setting the cs to 0x08 and the ds,es,fs,gs,ss to 0x10 but on user mode I am not setting the cs to 0x18 but the cs to 0x1B (0x18+0x03 (for ring 3)) but the gdt says that when the cs points the 4nd discription we are on ring 3 why to say it 2 times, the CPU cannot understand this with the first? Also on qemu when I am on user mode it says that the segment registers is on ring 3 but the eflags are saying that we are on ring 0. Maybe I need to do something and for that?
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