mariuszp wrote:
The power bit is set, just checked. However is my reset sequence correct?
Code:
sleep(100);
ehciRegs->ports[i] |= EHCI_PORT_RESET;
sleep(50);
ehciRegs->ports[i] &= ~EHCI_PORT_RESET;
I booted and looked at the results of your .ISO you sent me. It does the following:
Code:
00649062448d[EHCI ] register read from offset 0x0024: 0x0000000000000004 (len=4)
00649062448d[EHCI ] register write to offset 0x0024: 0x0000000000000004 (len=4)
00649090482d[EHCI ] register write to offset 0x0038: 0x0000000001D5E000 (len=4)
00649090482d[EHCI ] register read from offset 0x0020: 0x0000000000080001 (len=4)
00649090482d[EHCI ] register write to offset 0x0020: 0x0000000000080021 (len=4)
00649090509d[EHCI ] register read from offset 0x0024: 0x0000000000000000 (len=4)
... repeated for quite some time
(you should really set up interrupts. polling uses a lot of CPU/bus time)
00649090509d[EHCI ] register read from offset 0x0024: 0x0000000000000000 (len=4)
00649100000d[EHCI ] register read from offset 0x0024: 0x0000000000008000 (len=4)
00651049433d[EHCI ] register read from offset 0x0064: 0x000000000000100F (len=4)
00651049433d[EHCI ] register write to offset 0x0064: 0x000000000000100F (len=4)
00651049454d[EHCI ] register read from offset 0x0004: 0x0000000000103206 (len=4)
00656167034d[EHCI ] register read from offset 0x0064: 0x0000000000001005 (len=4)
00656167034d[EHCI ] register write to offset 0x0064: 0x0000000000001105 (len=4)
... repeated for quite some time. In fact, it never stops.
In the above code, you set the reset bit in the PORT0 register, then wait for it to become clear.
The controller won't ever clear it.
I misled you:
Ben wrote:
The reset can be complicated.
1) The USBSTS:HcHalted bit must be zero, hence, the schedule must be running
2) Set the Port Reset bit and clear the Port Enabled bit at the same time
3) Since this is a root hub, make sure you assert the reset for 50ms.
4) Wait for the bit to clear
5) Pause for TRSTRCY (recovery time)
I don't know where I got that from. The controller won't clear the bit, you must clear the bit.
I apologize for that, my mistake.So the above should be:
Ben wrote:
1) The USBSTS:HcHalted bit must be zero, hence, the schedule must be running
2) Set the Port Reset bit and clear the Port Enabled bit at the same time
3) Since this is a root hub, make sure you assert the reset for 50ms.
4) Clear the bit
5) Pause for TRSTRCY (recovery time)
Is VirtualBox clearing the bit and allowing your code to continue? If so, VirtualBox is in error.
Anyway, after fixing your code to not wait for the bit to be clear, it looks like your code works just fine. I wonder if VirtualBox is to blame, but I have my doubts. Here is the new results:
Code:
00614699990d[EHCI ] register read from offset 0x0024: 0x0000000000000000 (len=4)
00614699997d[EHCI ] register read from offset 0x0024: 0x0000000000000000 (len=4)
00614700004d[EHCI ] register read from offset 0x0024: 0x0000000000008000 (len=4)
00616649103d[EHCI ] register read from offset 0x0064: 0x000000000000100F (len=4)
00616649103d[EHCI ] register write to offset 0x0064: 0x000000000000100F (len=4)
00616649124d[EHCI ] register read from offset 0x0004: 0x0000000000103206 (len=4)
00621766708d[EHCI ] register read from offset 0x0064: 0x0000000000001005 (len=4)
00621766708d[EHCI ] register write to offset 0x0064: 0x0000000000001105 (len=4)
00621766708d[EHCI ] register read from offset 0x0064: 0x0000000000001005 (len=4)
00621766708d[EHCI ] register read from offset 0x0064: 0x0000000000001005 (len=4)
00621800000d[EHCI ] submit: qh 1d5e002 next 1d5e002 qtd 1d5f000 pid 2d len 8 (total 8) endp 0 ret 0
00621800000d[EHCI ] execute_complete: qhaddr 0x1d5e002, next 1d5e002, qtdaddr 0x1d5f000, status 0
00621800000d[EHCI ] updating tbytes to 0
00621800000d[USBMSD] USB_REQ_SET_ADDRESS:
00621800000d[EHCI ] submit: qh 1d5e002 next 1d5e002 qtd 1d5f020 pid 69 len 0 (total 0) endp 0 ret 0
00621800000d[EHCI ] execute_complete: qhaddr 0x1d5e002, next 1d5e002, qtdaddr 0x1d5f020, status 0
00621800000d[EHCI ] updating tbytes to 0
And now your results:
Code:
TOKEN WAS: 0x00080E80, TOKEN IS: 0x80000E00
TOKEN WAS: 0x00080E80, TOKEN IS: 0x80000E00
TOKEN WAS: 0x00080E80, TOKEN IS: 0x80000E00
The only thing I saw that might be in question is that your QHhorz pointer points back to the same QH instead of the next one in the list.
Fix your reset code to not wait for the bit to be clear (again, sorry about that) and run it on real hardware again.
Ben