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 Post subject: APIC not working for Application Processors in some cases
PostPosted: Tue Jul 18, 2017 12:43 pm 
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I am seeing a strange bug since some days ago: In my x86_64 kernel, I added APIC support to get the APIC timer to fire interruptions to all CPUs and, while in QEMU all works ok, in Bochs, VirtualBox and real hardware (my laptop) it fails for every Application Processor, while it works for the BootStrap Processor. I think the code used to enable it is not the cause because I use the same code for both cases.

I read the MSR 0x1b to get the base address (and get 0xfee00900 for the BSP and 0xfee00800 for the APs, as expected), and mask off undesired bits.
(BTW, are those addresses guaranteed to be the same for all cores?).

Basically the problem is that whenever I write to the APIC Entry Timer Register (and others: 0x320 - 0x370), I clear the mask bit, and when I read it again the mask bit is set again. e.g.: Initially it is 0x10000, I set it to 0x20030, I read 0x30030. To other regs: it is 0x10000, I write 0x31, I read 0x10031... I write to register 0xf0 the value 0x1ff to enable APIC. I did not setup IOAPIC, though.

I don't think it is a problem with the data sizes used for writing or reading, because for the BSP it works always (for the APs only in QEMU). What could be the cause? Any idea?


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 Post subject: Re: APIC not working for Application Processors in some case
PostPosted: Tue Jul 18, 2017 1:31 pm 
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Hi,

rod wrote:
I am seeing a strange bug since some days ago: In my x86_64 kernel, I added APIC support to get the APIC timer to fire interruptions to all CPUs and, while in QEMU all works ok, in Bochs, VirtualBox and real hardware (my laptop) it fails for every Application Processor, while it works for the BootStrap Processor.


Those words ("get the APIC timer to fire interruptions to all CPUs") don't quite make sense. There's a local APIC timer for each CPU (e.g. many local APIC timers and not "the local APIC timer"), and each local APIC timer is only able to send an IRQ to its own CPU (and no local APIC timer is able to broadcast an interrupt to all CPUs).

rod wrote:
I think the code used to enable it is not the cause because I use the same code for both cases.


I think that the code used to enable it is the cause (e.g. it fails to configure something that it should have, which just happens to have been left configured in the BSP by accident).

rod wrote:
I read the MSR 0x1b to get the base address (and get 0xfee00900 for the BSP and 0xfee00800 for the APs, as expected), and mask off undesired bits.


This is a bad idea (Intel's MSR may not exist on non-Intel CPUs and won't exist on some Intel CPUs either - e.g. 80486). Instead you should get the address of the local APIC from ACPI's tables or MultiProcessor Table.

rod wrote:
(BTW, are those addresses guaranteed to be the same for all cores?).


Yes (guaranteed by firmware, not by CPU manufacturer).

rod wrote:
Basically the problem is that whenever I write to the APIC Entry Timer Register (and others: 0x320 - 0x370), I clear the mask bit, and when I read it again the mask bit is set again. e.g.: Initially it is 0x10000, I set it to 0x20030, I read 0x30030. To other regs: it is 0x10000, I write 0x31, I read 0x10031... I write to register 0xf0 the value 0x1ff to enable APIC. I did not setup IOAPIC, though.


Did you enable the local APIC in the Spurious Interrupt Vector Register (bit 8 at "base +0x00F0")?


Cheers,

Brendan

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 Post subject: Re: APIC not working for Application Processors in some case
PostPosted: Tue Jul 18, 2017 1:56 pm 
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Joined: Mon Feb 10, 2014 7:42 am
Posts: 21
Oh, thanks, I solved it! It was a silly error.
Brendan wrote:
This is a bad idea (Intel's MSR may not exist on non-Intel CPUs and won't exist on some Intel CPUs either - e.g. 80486). Instead you should get the address of the local APIC from ACPI's tables or MultiProcessor Table.

Ok. I see, I need to parse those tables, but by now it was simpler to read the MSR.
Brendan wrote:
Did you enable the local APIC in the Spurious Interrupt Vector Register (bit 8 at "base +0x00F0")?

That was the cause! I did set that register, but I did it *after* trying to unmask the timer. So I moved that code to the beggining of the enable procedure, and.. works!. Thanks for the pointers! It happens that the BSP had it enabled from the beggining and the APs did not, that was the problem.


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