Hi,
Korona wrote:
On ICH (at least on ICH7, I assume not much changed before/after that) there is a chipset specific (documented) register that controls if PCI interrupts are routed to the I/O APIC or XT PIC. _PIC manipulates this register. Simultaneously receiving IRQs at both PICs is not possible.
It would be nice to see an AML disassembly; but as far as I can tell you're talking about the "PIRQx Route Control registers" which are supposed to described by a table defined by the "PCI IRQ Routing Table Specification" (that pre-dates ACPI). Unfortunately this specification is hard to obtain now (it was on Microsoft's developer site, but Microsoft seems to have removed it). Note that in this case, there's no real reason that firmware can't leave PCI IRQs connected to PIC inputs (via. "PIRQx Router") and connected to IO APIC inputs at the same time; such that an OS needn't touch anything to use PIC or IO APIC or both (other than PIC masks and IO APIC input masks).
Korona wrote:
Other chipsets may behave differently though.
For "older computers" I mostly meant "about 2005 or older". For a crude timeline; before about 2000 ACPI didn't really exist (or was too unreliable to use) and all multi-CPU 80x86 computers (and some that were single CPU but had APICs) used the MultiProcessor Specification, then from about 2000 to 2005 the MultiProcessor Specification mostly remained usable for backward compatibility.
Cheers,
Brendan