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 Post subject: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Tue Jun 06, 2017 5:34 pm 
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I've successfully programmed a simple APIC setup, detecting IO APICs from the MP tables and redirecting the IRQs I want to the local APIC. Now I've run into a problem, how can I deal with the situation where the CPU has a local APIC, but there is no IO APIC?
I didn't see anything in the Intel Local APIC or IO APIC manuals about a setup without an IO APIC, so I'm assuming I'll need to fall back to the 8259 PIC to receive IRQs. Is this the proper method, or have I somehow overlooked how to use hardware interrupts directly with the local APIC?


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 Post subject: Re: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Tue Jun 06, 2017 8:37 pm 
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I think you misunderstood the concept of how interrupts are sent using the I/O APIC. Each CPU core has one local APIC, and this local APIC has an "APIC ID", which is a unique integer that differentiates it from other local APICs. You probably already know this, because you mention the MP tables. Now, the chipset has an external circuit called the I/O APIC, which receives interrupts from devices and redirects them to the CPU local APICs, which is what you do when you configure the I/O APIC. In other words, the CPU's local APIC is not directly connected to the regular devices, and doesn't work as a "public" interrupt controller.

To answer your question: if you encounter a PC with a local APIC but no I/O APIC, you must use the legacy dual-installation PIC.

As a side note, the MP tables are deprecated and you should use ACPI instead. Searching for ACPI tables is also very simple and has the same idea (just searching for byte patterns in RAM). The Wiki has sufficient information on ACPI to get you started. Specifically, you'll want the ACPI MADT (aka APIC) table.

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 Post subject: Re: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Tue Jun 06, 2017 9:33 pm 
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This answers my question perfectly, thank you. I did understand how the interrupts were sent when an IOAPIC was installed, but I misunderstood some articles to imply the PIC was incompatible with all APIC usage rather than only the IO APIC.
And yes, I'll be adding ACPI support soon, I just dove straight into writing a MP tables parser before I realized ACPI tables were simple as well.


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 Post subject: Re: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Wed Jun 07, 2017 2:29 am 
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It should also be noted that the I/O APIC will not work on real hardware (at least on ICH chipsets) unless you invoke the _PIC AML control method (or poke chipsets registers manually). You basically need an AML interpreter (e.g. ACPICA) or chipset driver to use the I/O APIC.

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 Post subject: Re: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Wed Jun 07, 2017 6:35 am 
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Hi,

Korona wrote:
It should also be noted that the I/O APIC will not work on real hardware (at least on ICH chipsets) unless you invoke the _PIC AML control method (or poke chipsets registers manually). You basically need an AML interpreter (e.g. ACPICA) or chipset driver to use the I/O APIC.


Maybe.

For older computers (which had to be backward compatible with OSs that used the MultiProcessor Specification tables that don't use ACPI) the IO APIC has to be usable without calling ACPI's _PIC method. In this case, the _PIC method would only be able to set/change variables used by other AML code, but if the OS isn't using other AML code that wouldn't matter.

For newer computers that don't support the MultiProcessor Specification tables (and therefore aren't backward compatible with OSs that used the MultiProcessor Specification tables) I'd expect a mixture - some where calling the _PIC method only effects variables used by other AML code (where you don't strictly need to bother if you don't use other AML code), and some where it does effect the chipset in some way (where you'd need to use the _PIC method even if you don't use any other AML code). Of course for these cases there's also a related problem: you can't easily figure out which devices use which IO APIC inputs either; so you end up wanting AML (or motherboard driver) for multiple reasons (to call _PIC in case it matters, and to determine which devices use which IO APIC inputs).


Cheers,

Brendan

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 Post subject: Re: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Wed Jun 07, 2017 9:12 am 
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On ICH (at least on ICH7, I assume not much changed before/after that) there is a chipset specific (documented) register that controls if PCI interrupts are routed to the I/O APIC or XT PIC. _PIC manipulates this register. Simultaneously receiving IRQs at both PICs is not possible.

Other chipsets may behave differently though.

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 Post subject: Re: Hardware interrupts with a Local APIC but no IO APIC?
PostPosted: Wed Jun 07, 2017 10:05 am 
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Hi,

Korona wrote:
On ICH (at least on ICH7, I assume not much changed before/after that) there is a chipset specific (documented) register that controls if PCI interrupts are routed to the I/O APIC or XT PIC. _PIC manipulates this register. Simultaneously receiving IRQs at both PICs is not possible.


It would be nice to see an AML disassembly; but as far as I can tell you're talking about the "PIRQx Route Control registers" which are supposed to described by a table defined by the "PCI IRQ Routing Table Specification" (that pre-dates ACPI). Unfortunately this specification is hard to obtain now (it was on Microsoft's developer site, but Microsoft seems to have removed it). Note that in this case, there's no real reason that firmware can't leave PCI IRQs connected to PIC inputs (via. "PIRQx Router") and connected to IO APIC inputs at the same time; such that an OS needn't touch anything to use PIC or IO APIC or both (other than PIC masks and IO APIC input masks).

Korona wrote:
Other chipsets may behave differently though.


For "older computers" I mostly meant "about 2005 or older". For a crude timeline; before about 2000 ACPI didn't really exist (or was too unreliable to use) and all multi-CPU 80x86 computers (and some that were single CPU but had APICs) used the MultiProcessor Specification, then from about 2000 to 2005 the MultiProcessor Specification mostly remained usable for backward compatibility.


Cheers,

Brendan

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