Korona wrote:
As far as I understand the architectural behavior of INIT is resetting the processor (which includes resetting CS:IP to 0xFFFFFFF0) and executing the BIOS ROM code at this address. Is this correct?
No. That's the behavior of INIT on systems using the 82489DX APIC, which will be 486 and early (<75MHz) Pentiums only. On everything newer than that, INIT halts the CPU and enters the wait-for-SIPI state.
Korona wrote:
The architectural behavior of SIPI is leaving the wait-for-SIPI state and setting IP to the page that is determined by the SIPI vector. Again: Is this understanding correct?
IP is always 0, it sets CS according to the SIPI. Other than that, you're correct.
Korona wrote:
Why do processors need two SIPIs at all?
Because Intel says so. I don't think they've ever given a specific reason for it.
Korona wrote:
Is the second SIPI redundant and only necessary in case of a delivery failure?
Most likely.
Korona wrote:
Are there processors that only exit wait-for-SIPI after two (correctly delivered) SIPIs?
I don't know if anyone has ever specifically looked for one.
Korona wrote:
Are there non-82489DX systems that need the warm-reset?
No. The warm reset is only used on systems with the 82489DX, since those systems don't support SIPI.
Korona wrote:
Does the BIOS enter wait-for-SIPI if the shutdown code is set to warm-reset?
No. CPUs with integrated APICs enter wait-for-SIPI immediately upon receiving an INIT IPI, and the BIOS isn't involved at all. CPUs using the 82489DX reset upon receiving an INIT IPI and begin executing BIOS code, which checks the shutdown code and jumps to the warm reset vector.