I'm developing a secure (text mode) O/S on x-86. It's all going well, boot loader written, 32 bit protected mode running (thanks to your pages and others). I then realised I need to enter 64 bit long mode for memory and processing reasons. The cr registers I can understand but the paging tables are a little difficult to get my head around. The O/S will be the only process running and will only use one processor for now. What I want to have is (in 1GB page translation mode) is all of memory (4gb+) paged and a 100MB code segment with the rest given over to data. Do I just set up a blank PML4E table and 4 entries in the PDPE table (4 1gb pages) and then make two 64 bit GDT tables for the code and data bits? I'd be most grateful for any help on this subject as there doesn't seem to be any help on what I want to do and otherwise I can see weeks of triple faults ahead!
As a bare minimum; you'd need:
- A PML4, with one entry (that points to a PDPT)
- A PDPT, with four entries (one for each "1 GiB page")
- A GDT with at least 3 entries (a "NULL" entry that the CPU won't touch, plus one for 64-bit code and another for data).