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 Post subject: VIA Nano CPUID manuals
PostPosted: Thu Feb 21, 2013 10:11 am 
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Joined: Thu Feb 21, 2013 9:49 am
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Hi all,

Does anyone knows where do i find VIA Nano CPUID manuals. I searched all over the internet, but only found manuals from 2004. Or someone knows how to identify their CPUs. Any help and i'll be very grateful.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Thu Feb 21, 2013 10:52 am 
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Hi,

dancer wrote:
Does anyone knows where do i find VIA Nano CPUID manuals. I searched all over the internet, but only found manuals from 2004. Or someone knows how to identify their CPUs. Any help and i'll be very grateful.


Sadly, VIA's documentation is very hard to get hold of, and I haven't managed to find any documentation for any of their CPUs that are newer than C3. I'm not sure if you need to sign NDAs, or become an "Embedded Partner" or if it doesn't exist in English (e.g. and only exists in Taiwanese), or if documentation doesn't exist at all.

Worse, I'm expecting VIA's 80x86 CPUs to disappear this year - according to the wikipedia page "in 2003 VIA arrived at an agreement with Intel that allowed for a ten year patent cross license, enabling VIA to continue to design and manufacture x86 compatible CPUs". I don't think this cross-licencing agreement will be renewed. If this happens documentation for their CPUs will be even harder to get.


Cheers,

Brendan

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For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Thu Feb 21, 2013 11:31 am 
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I'm searching this documentation for some time. I sometimes doubt if VIA Nano CPU at all exits. Never seen it, never heard about it. Only know it from the internet. Now i know a bit more about it. Thanks Brendan.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Thu Feb 21, 2013 12:01 pm 
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Hi,

dancer wrote:
I'm searching this documentation for some time. I sometimes doubt if VIA Nano CPU at all exits. Never seen it, never heard about it. Only know it from the internet. Now i know a bit more about it. Thanks Brendan.


They do exist - I have one here (an older single-core Nano that took me about 6 months to find after the CPU was officially announced). ;)


Cheers,

Brendan

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For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Thu Feb 21, 2013 4:15 pm 
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I have a VIA Nano embedded board running my home heat control system. Their CPU is a typical CPU compatible with older motherboards with PIC and similar. I don't know why you would need a manual for the CPU? I even managed to write an audio driver for their chipsets, so at last at that point the chipset manuals were available.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Thu Feb 21, 2013 8:01 pm 
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Hi,

rdos wrote:
I don't know why you would need a manual for the CPU?


If I had a manual, the first thing I'd do is look for "non-standard" features that my OS could take advantage of. I know that VIA's CPUs typically do have "VIA PadLock Security Engine" (crypto random number generator, AES, SHA, etc), but I'm not sure if they've extended it, or if they've added anything new/unrelated.

The next thing I'd do is try to determine how compatible it is with other CPU manufacturer's products. For example, I know Nano has hardware virtualisation and I think it's mostly compatible with Intel's hardware virtualisation (but don't actually know how compatible it is). I assume Nano has some sort of performance monitoring MSRs and machine check, but (as these tend to depend heavily on the design of the chip) I'd doubt they're compatible with anything. Another example is figuring out how to detect cache details using CPUID (if it's different, or the same as AMD, or if you need to use one of Intel's methods and which one).

Finally I'd look for errata - try to find out if there's any work-arounds an OS needs to implement to ensure the CPU behaves correctly. I typically implement relatively extensive support for this in my OSs; where "work-arounds" could mean fixing information from CPUID, or extra support in the kernel, or disabling/refusing to use certain CPU features, or setting flags to warn end-users that there's problems that can't be worked around, or in extreme cases (not happened yet) maybe even refusing to boot.


Cheers,

Brendan

_________________
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Fri Feb 22, 2013 2:46 am 
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Joined: Thu Feb 21, 2013 9:49 am
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I need that manual because i'm writting CPUID program. I'm not OS developer. I've persumed that you will know things like that. I'm not familiar with all things you're talking about. I'm beginner programmer. Thanks for tips.


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 Post subject: Re: VIA Nano CPUID manuals
PostPosted: Tue Apr 16, 2013 2:39 am 
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The manual you want is VIA_Nano_Processor_X2X4_BIOS_Guide_2_47.pdf or later which is only available is you have an NDA and even then it's quite hard to get hold of :cry:.

You may find the following dump helpful.

case 15:
cpu->technology = smb->slb.tec_065;

switch( cpu->stepping )
{
case 0: cpu->step = TEXT( " [A0]" ); break; // CPU Stepping
case 1: cpu->step = TEXT( " [A1]" ); break;
case 2: cpu->step = TEXT( " [A2]" ); break;
case 3: cpu->step = TEXT( " [A3]" ); break;
case 8: cpu->step = TEXT( " [A1]" ); break;
case 10: cpu->step = TEXT( " [A2]" ); break;
case 12: cpu->step = TEXT( " [A1]" ); break;
case 13: cpu->step = TEXT( " [A2]" ); break;
}

if( cpu->stepping >= 0x0C )
{
cpu->codename = cpu->count > 2 ? TEXT( " (Isaiah, CNQ)" )
: TEXT( " (Isaiah, CNC)" );
cpu->technology = smb->slb.tec_040;
}
else
if( cpu->stepping >= 0x08 )
{
cpu->codename = TEXT( " (Isaiah, CNB)" );
}
else
{
cpu->codename = TEXT( " (Isaiah, CNA)" );
}

stprintf( cpu->dpn, TEXT( "VIA%s%s" ), cpu->count >= 4 ? TEXT( " QuadCore" ) :
cpu->count >= 3 ? TEXT( " Nano X3" ) :
cpu->count >= 2 ? TEXT( " Nano X2" ) : TEXT( " Nano" ),
cpu->codename );
break;


[CPUID CPU-0] <- SIV64X - System Information Viewer V4.37 Beta-06 VX11::via

CPU-0 VIA QuadCore L4700 @ 1.2+ GHz (VIA QuadCore (Isaiah, CNQ)) [A2] STK 1466MHz CPU 1066MHz FSB 266MHz L2 1066MHz WIN 1466MHz

CPUID EAX EBX ECX EDX
00000000 0000000A 746E6543 736C7561 48727561 [Y]"CentaurHauls"
00000001 000006FD 00080800 008863A9 BFC9FBFF [Y]09 APIC 0x00 [Y]16 Count 8 [Y]08 CX8 [Y]05 MSR [Y]04 TSC [Y]03 PSE
00000002 02B3B001 00000000 00000000 2C04307D [Y]7D L2U 8-way 64-byte 2MB [Y]30 L1C 8-way 64-byte 32KB
[Y]2C L1D 8-way 64-byte 32KB
00000003 00000000 00000000 00000000 00000000
00000004 1C000021 03C0003F 0000003F 00000000 [Y]L1 Data 64KB APICs 8 Share 1 00 Ways 16 Phys 1 Line 64 Sets 64
00000004 1C000022 03C0003F 0000003F 00000000 [Y]L1 Code 64KB APICs 8 Share 1 00 Ways 16 Phys 1 Line 64 Sets 64
00000004 1C000043 07C0003F 000001FF 00000000 [Y]L2 Unified 1MB APICs 8 Share 1 00 Ways 32 Phys 1 Line 64 Sets 512
00000005 00000040 00000040 00000003 00022220
00000006 00000002 00000000 00000000 00000000
00000007 00000000 00000000 00000000 00000000
00000008 00000000 00000000 00000000 00000000
00000009 00000000 00000000 00000000 00000000
0000000A 06280202 00000000 00000000 00000503 [Y]2 / CPU Events 6 [Y]Width 40 Revision 2 [Y]Fixed 3 [Y]Width 40

80000000 80000008 00000000 00000000 00000000 [_]" "
80000001 00000000 00000000 00000001 20100800 [Y]29 x64 Support [_]27 RDTSCP Support [_]26 1GB Large Page [Y]20 Execute Disable
80000002 20202020 20202020 20202020 20202020
80000003 49562020 75512041 6F436461 4C206572
80000004 30303734 31204020 202B322E 007A4847 [Y]" VIA QuadCore L4700 @ 1.2+ GHz"
80000005 00000000 08800880 40100140 40100140 [Y]L1C 64KB 16-way 64-byte line [Y]L1D 64KB 16-way 64-byte line
80000006 00000000 00000000 04008140 00000000 [Y]L2U 1MB 16-way 64-byte line [_]L3U 0KB 0-way 0-byte line
80000007 00000000 00000000 00000000 00000000 [_]09 CPB Perf Boost [_]08 TSC Invatiant [_]02 VID Control [_]01 FID Control
80000008 00003024 00000000 00000000 00000000 [Y]Physical 36 64GB [Y]Virtual 48 256TB [_]Cores 1 (8)

C0000000 C0000004 00000000 00000000 00000000 [_]" "
C0000001 000006FD 00000000 00000000 1EC33DCC [_]09 APIC 0x00 [_]16 Count 0
C0000002 00000000 00000000 00000000 00000000
C0000003 00000000 00000000 00000000 00000000
C0000004 00000024 08000854 08520B65 00000000


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