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 Post subject: AMD64 Translation Cache Extension
PostPosted: Tue Aug 01, 2017 5:31 am 
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Hello,

I have been reading the AMD64 documentation found here: http://developer.amd.com/resources/developer-guides-manuals/. In volume 2, it describes how the Extended Feature Enable Register contains a bit (15) which will enable "translation cache extension". By the looks of it this will increase processor performance as invalidations of page table entries will not cause all upper-level table entries to be removed from the TLB's cache, rather only the upper-level entries that lead to the invalidated page.

However, I am having difficulty working out how to detect the presence of the feature. It claims that "CPUID Fn8000_0001_ECX[TCE]" indicates that the extension will be present, but on consultation of volume 3 which contains details of the information returned by the CPUID instruction, I am unable to find information about to which bit "TCE" refers. In fact, searching this volume's PDF yields no mention of the extension that I could see at all. Intel's software developer manuals seem to contain no reference to the extension, so I'm guessing that the feature is only available on AMD processors.

This has left me with a few questions. I haven't been able to find any information about it on the internet, so if anyone knows how I could detect this feature, or knows anything about it at all (e.g. was it deprecated?, is it only a proposed feature?, etc.), guidance would be appreciated. :)

Thanks.


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 Post subject: Re: AMD64 Translation Cache Extension
PostPosted: Tue Aug 01, 2017 5:51 am 
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Looks like AMD forgot to update that part of the manual.

You can see the CPUID.TCE bit described in several other manuals, including the processor programming reference for family 17h and (at least some of) the BIOS and kernel developer's guides for family 15h.

It's also listed on sandpile.org.

(All of these sources agree: it's bit 17.)


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