Hi,
Izzette wrote:
Yeah, I send an EOI to the master in the IRQ0,1,3-7 handlers, and one to the slave in IRQ8-15 handlers, after re-enabling interrupts (I'm using interrupt gates not trap gates), but before IRET.
If the slave sees an IRQ, then it's a little bit like the slave triggers "IRQ2" on the master (except the master doesn't send the "interrupt vector" to the CPU and lets the slave send it); which means that you need to send an EOI to the slave (to clear its IRQ8) and then send an EOI to the master (to clear its IRQ2).
If you don't send EOI to master, then the PIC chip's "IRQ priorities" prevent lower priority IRQs (IRQs 8, 9, 10, 11, 12, 13, 14, 15, 3, 4, 5, 6 and 7) from being sent to the CPU, but higher priority IRQs (IRQs 0 and 1) do keep working.
Note: While browsing your code I also noticed that you don't handle spurious IRQs properly. If IRQ7 occurs you should ask the master PIC if it's a spurious IRQ and ignore it (without sending EOI) if it is; and if IRQ15 occurs you should ask the slave PIC if it's a spurious IRQ and if it is only send EOI to the master PIC but not the slave PIC.
Cheers,
Brendan